The present invention relates generally to design automation, and relates more particularly to statistical timing of integrated circuit (IC) chips.
When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Selection of these paths is complicated by the presence of process variations. Because of these variations, different paths can be critical in different chips. That is, a path that is critical in one chip may not be critical in another chip, and vice versa. As such, selection of the paths that have a higher probability of being critical is typically a goal.
Conventional test pattern generation tools select these paths based on a single-layer process space coverage metric. As such, some points (i.e., combinations of process parameters) in the process space may only be covered by one path. If that path is not sensitizable (i.e., not capable of being tested), then these points in the process space may be left uncovered by the at-speed testing, resulting in a loss of test quality.
Thus, there is a need in the art for a method and apparatus for covering a multilayer process space during at-speed testing.